| 摘要 |
<p>A semiconductor memory device includes an address change detection circuit (TRo. TR,...) and a pulse width control circuit (PWC). The pulse width control circuit (PWC) inhibits the passage of write enable signals (WE) having a short pulse width for a predetermined time period after a change of address has occurred. After the predetermined period has elapsed the operation of the pulse width control circuit (PWC) is overridden and thus the write cycle time is reduced.</p> |
