发明名称 |
An information processing apparatus having an instruction prefetch circuit. |
摘要 |
<p>An information processing apparatus with an instruction prefetch unit is disclosed, in which a CPU operation can be stopped at a desired address in response to a break signal. The instruction prefetch unit has an instruction prefetch circuit storing an instruction and an indication register storing the break signal. A read operation and a write operation of the indication register are executed together with those of the instruction prefetch circuit. Thus, a break point can be set a desired address by using the indication register, and the break operation can be correctly performed without complex hardware means.</p> |
申请公布号 |
EP0166431(A2) |
申请公布日期 |
1986.01.02 |
申请号 |
EP19850107889 |
申请日期 |
1985.06.26 |
申请人 |
NEC CORPORATION |
发明人 |
HARIGAI, HISAO;TAKAHASHI, TOSHIYA;IWASAKI, TAMOTSU |
分类号 |
G06F11/28;G06F9/38;G06F9/48;(IPC1-7):G06F9/38 |
主分类号 |
G06F11/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|