| 摘要 |
<p>A semiconductor memory device includes at least a pair of bit lines (BL, BL), a word line (WL), a pair of load transistors each connected to the bit lines (Q5, Q6), a memory cell (MC) connected to the bit lines and the word line and selected by an address signal, and an equalizing circuit (EQ') connected between each of the bit lines. According to the present invention, the equalizing circuit comprises a P-channel type MIS transistor (Qp) and a N-channel type MIS transistor (QN) each connected in parallel. The P-channel type MIS transistor and the N-channel type MIS transistor are temporarily turned ON in response to a change of the address signal. In this way complete equalization of the respective potentials of the two bit lines can be achieved and access time to the memory cell can thereby be shortened as compared with the prior art.</p> |
