METHOD FOR GENERATING TEST PATTERN FOR TESTING SEMICONDUCTOR MEMORY

摘要

PURPOSE: A method is provided to generate a test pattern compatible with a test equipment by applying a pattern generated by a TPG(Test Pattern Generator) within an MBT(Memory Burn-in Tester) to a device to be tested when a TSC(Test Station Controller) applies a pattern program to the MBT. CONSTITUTION: A method for generating a test pattern includes the first through fifth steps. The first step is to judge whether a TPG(Test Pattern Generator)(21) is enabled or not when the pattern program is downloaded from a TSC(Test Station Controller)(30) to the TPG. The second step is to read a micro-code address to be performed next from a micro-code address register in the TPG when the TPG is enabled. The third step is to patch an instruction code from a micro-code memory in the TPG by referring to the micro-code address. The fourth step is to generate pattern data and a scramble address by performing an operation when the instruction code is an OP code and then to write the generated pattern data to a DUT(Device Under Test). The fifth step is to stand by until next OP code operates when the instruction code is not an OP code.