| 摘要 |
<p>A bus control system for transferring a command or data between two integrated circuit devices (hereafter LSIs (A and B)) wherein an LSI (A) for issuing a command or data (issuing side LSI (A)) outputs a strobe signal (CMD_STRB), which indicates that a valid command or data was issued, to an LSI (B) which receives the command or data (receiving side LSI (B)), and the receiving side LSI (B) outputs a signal, which notifies that command processing has been completed (command ready signal (CMD_READY)), to the issuing side LSI (A). The issuing side LSI (A) comprises a counter (18) where a value to indicate the number of commands which the receiving side LSI (B) can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter value is decremented when a command or data is issued, the counter value is incremented when the ready signal (CMD_READY) is received, and issuing a command or data is inhibited when the counter value becomes "0". Therefore the issuing side LSI (A) can issue a command or data to the receiving side LSI (B) without confirming a busy signal from the receiving side LSI (A). <IMAGE></p> |
