发明名称 Method and apparatus for generating test sequence
摘要 <p>Disclosed is a method and apparatus for generating a test sequence to test a fault in a digital circuit. According to this method and apparatus, when a fault propagation process for a fault, for which a test sequence is generated is not successful, at least a segment of a path to propagate the effects of the fault is memorized as illegal information. And the fault propagation process is restarted for the same fault without selecting the illegal information. Hence, the chance of a successful fault propagation process is increased, which leads to the improvement of the fault coverage. In addition, according to the apparatus and method, it is detected whether a state transition goes into a loop (i.e., two identical states exist) in the state initialization process and then the process is restarted by defining the state caused the loop as an illegal state. Hence, the chance of a successful state initialization process is increased, which leads to the improvement of the fault coverage.</p>
申请公布号 EP1132749(A2) 申请公布日期 2001.09.12
申请号 EP20000128551 申请日期 1993.03.26
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 HOSOKAWA, TOSHINORI
分类号 G01R31/3183;(IPC1-7):G01R31/318;G06F11/263 主分类号 G01R31/3183
代理机构 代理人
主权项
地址