发明名称 DIGITAL SIGNAL REPRODUCING SYSTEM
摘要 PURPOSE:To obtain a digital signal reproduction system having the capacity of reducing final error of a system by adding a condition of >=1-bit error as a synchronizing bit detection system. CONSTITUTION:A ROM is provided in a synchronism detection circuit 3 and nine ways of data in total, the state of error in each bit of a synchronizing character data, that is, 1-bit error state, are written in advance in the said ROM in addition to asynchronizing character data. When a data inputted to the synchronism detection circuit 3 is coincident with any of nine kinds of data, a logical ''1'' level signal is outputted from an output terminal D to a code detection circuit 4, and a logical ''0'' level signal is outputted when the data is a data other than the nine kinds. When a logical ''1'' level signal is inputted to the code detection cicuit 4, a serial data inputted from a terminal A is read and when no error exists after error correction, an 8-bit parallel data is outputted via a terminal C.
申请公布号 JPS60264136(A) 申请公布日期 1985.12.27
申请号 JP19840121083 申请日期 1984.06.12
申请人 SHARP KK 发明人 OOTA AKIO
分类号 H04L1/00;H04L7/00;H04L7/04;H04L7/08 主分类号 H04L1/00
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