发明名称 ERROR CORRECTION DECODER
摘要 PURPOSE:To obtain an error correction decoder detecting an error not corrected when the error takes place on a transmission line by deciding it as detection of an error when an output of a merge detecting circuit shows non-merge and extracting a decoded output from the final stage of a path memory. CONSTITUTION:The path memory of a merge detecting circuit 405 stores a path connected in 4 ways of states (0, 0), (0, 1), (0, 1) and (1, 1). The path information corresponding to each state at the final stage is inputted respectively from terminals 500, 501, 502 and 503. When merge takes place, since the path after merge with respect to all states is the same, the input from the terminals 500, 501, 502 and 503 is all identical. Thus, the merge detection circuit 405 has only to detect whether the four inputs are all identical or not. An output of an exlcusive OR 506 goes to logical ''0'' when merge takes place and goes to logical ''1'' when no merge occurs, which allows merge detection. An error is detected through the detection of merge.
申请公布号 JPS60264125(A) 申请公布日期 1985.12.27
申请号 JP19840121394 申请日期 1984.06.13
申请人 NIPPON DENKI KK 发明人 FURUYA YUKITSUNA
分类号 H03M13/23 主分类号 H03M13/23
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