| 摘要 |
PURPOSE:To increase the number of delay stage and to make the time length of a signal possible for processing long by connecting respectively n-set of transversal filters and (n-1)-set of delay circuits in cascade, inputting an output of the delay circuits to the filters, setting a weight coefficient series to the filters and adding the outputs. CONSTITUTION:The weight coefficient series divided into (n) blocks are set to the n-set of transversal filters 151-15n, each delay time of the (n-1)-set of the delay circuits 161-16n-1 is set equal to the delay time by the delay stage of each filter and a signal IN is fed to the circuit 161 and the filter 151. Outputs of the circuit 161 and succeeding circuits are fed respectively as input signals to the filter 152 and succeeding filters. Outputs of each filter are added by an adder 17 and the result becomes an output signal. Through the constitution above, an output signal OUT is equivalent to that of the filters to which the weight coefficient series for the (n) blocks' share are set. Thus, the time length of the signal possible for processing is prolonged. |
