发明名称 |
Memory circuit having a plurality of cell arrays. |
摘要 |
<p>A semiconductor memory circuit which can operate with reduced value of peak currents. The memory circuit includes two or more memory cell arrays each having a plurality of memory cells and a peripheral circuit for achieving selective access operation is provided for each array. At least a timing signal and its delayed timing signals are generated in response to a control signal. Both of the timing signal and the delayed timing signal are used to enable the peripheral circuits at different timing.</p> |
申请公布号 |
EP0165612(A2) |
申请公布日期 |
1985.12.27 |
申请号 |
EP19850107654 |
申请日期 |
1985.06.20 |
申请人 |
NEC CORPORATION |
发明人 |
TADA, KAZUHIRO |
分类号 |
G11C11/401;G11C7/22;G11C8/18;G11C11/407;(IPC1-7):G11C7/00;G11C11/40;G11C8/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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