发明名称 MEMORY DEVICE
摘要 <p>PURPOSE:To minimize the power supply capacity to a memory device by using a suppressing circuit which resets an FF of a memory element selection circuit with an incorporated initial condition setting circuit and holds the output given from said element selection circuit until the reset mode is through. CONSTITUTION:When an indication is given to a power supply control circuit 1 for application of the power supply, the power supply of a power supply circuit 2 is applied for generation of a DC power supply. When the DC power supply reaches a standard level, a clock signal, a shift mode designating signal and the shift-in data are applied to a memory element selecting circuit 5 from an initial condition setting circuit 3 via a switch circuit 4. The (n) pieces of FF51-5n of the circuit 5 are reset successively for each arrival of clock. Then all FFs are reset when an action start signal (b) is produced. Thus any of memory element trains of a memory circuit 7 is never actuated even though the gate of a suppressing circuit 6 is opened with the signal (b).</p>
申请公布号 JPS60262228(A) 申请公布日期 1985.12.25
申请号 JP19840116932 申请日期 1984.06.07
申请人 NIPPON DENKI KK 发明人 SATOU TOSHIHIKO
分类号 G06F1/26;G06F1/00;G06F11/34;G11C11/41;G11C11/413 主分类号 G06F1/26
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