| 摘要 |
A pipelining information processor which includes a memory, an instruction buffer, an execution stage, a logical address generator coupled with the instruction buffer, a physical address generator, and logic for fetching an instruction from the instruction buffer to the execution stage. The input to the physical address generator is selected by a selector as either a logical address of the operand of a prefetched instruction or a logical address of an instruction to be prefetched. If the prefetched instruction requires a memory access, the logical address of its operand is selected, otherwise the logical address of a new instruction to be prefetched is selected. Control logic sequentially moves instruction addresses through the selector, the instruction buffer, the logical address generator, and the physical address generator so that logical address generation, physical address modification, fetching a prefetched instruction from the instruction buffer to the execution stage, and execution may occur in parallel on successive instructions.
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