Phase-locked loop circuit

摘要

The phase-locked loop circuit of the present invention has a frequency dividing circuit which is reset in response to a reset signal that is generated based on said first frequency divided signal generated by dividing a frequency of a reference clock signal and an output signal output from a voltage controlled oscillator. The phase-locked loop circuit of the present invention can adjust the frequency and the phase of the output signal of the voltage controlled oscillator to that of the reference clock signal in a short time.