| 摘要 |
PURPOSE:To increase the independent characteristics of a virtual address space for address conversion of an information processor applying a multiplex virtual address system by invalidating the effect of a bit (c) to a specific virtual address space VS and allotting different programs or data to the virtual addresses which are used with the allotment of common programs or data for other plural spaces VS. CONSTITUTION:When VS1 or VS2 is switched to VS3, a control program sets 3 as VSID11 of a register 9, the head address of an address conversion table corresponding to the VS3 as ATO10 and 1 to an I bit 12 since the VS3 has no program nor data 4 common to the VS1 or VS2. As a result, the output of an AND gate 22 is set at 0 regardless of (c) bit 17. Then a TLB entry which has VS15 coincident with VA18 and VSID14 coincident with the VSID11 of the TR9 (3 in this case) can be used for address conversion of the VA18. In other words, only (3,a,delta,c=0) can be used for the conversion of a virtual address (a). Then (1,a,alpha,c=1) or (2,a,alpha,c=1) is never used by mistake even though they remain within a TLB. |
