发明名称 COMMUNICATION CONTROL SYSTEM BETWEEN PROCESSORS
摘要 PURPOSE:To attain direct access to main control processor for the communication area of the memory of a sub ordinate control processor by sending a request for communication from the main control processor and placing the subordinate control processor in a termporary stop state. CONSTITUTION:The main control processor MPU sends communication request information to the subordinate control processor SPU1. The subrodinate control processor SPU1 sends communication ready information to an information line m1 and holds itself in a temporary suspending stop state. The communication ready information of the information line m1 opens a bus gate BG1 corresponding to the subordinate control processor SPU1. Consequently, the main control processor MPU attains direct access to the memory M1 of the subordinate control processor SPU1. When the communication ready information of the information line m1 is ceased, the bus gate BG1 is closed and the communication ready information of the information line l1 is also ceased. Thus, communication control over all subordinate control processors SPU1-SPUn is performed.
申请公布号 JPS60258669(A) 申请公布日期 1985.12.20
申请号 JP19840115818 申请日期 1984.06.06
申请人 MEISEI DENKI KK 发明人 TOMINAGA YOSHINOBU;HOUJIYOU KATSUO;SHIGETA YUKIO;KOBAYASHI HANJI
分类号 H04Q3/545;G06F13/28;G06F13/38;G06F15/16;G06F15/17;G06F15/177 主分类号 H04Q3/545
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