| 摘要 |
<p>PURPOSE:To reduce the operation processing time, by stopping the operation of one cycle, after the execution of operation with a given number of cycles continuously, in a processing group in which a variable minimum clock period is slightly longer than the machine cycle time. CONSTITUTION:Three-digit of comparison bits COMP 0, 1 and 2 and 3-digit counter bits CNT 0, 1, 2 are inputted to a comparison section 21, and when the comparison bits and the counter bits are coincident at AND gates 31-3-31-7, a logical 0 is outputted as the output of the comparison section 31. A clock signal stop section 32 receives logical 0 from the comparison section 31, then the output is taken to logical 1 according to the logical 0 of a clock signal -CLK inputted to a clock stop section 32 to inhibit the passage of the clock signal -CLK to an AND gate 35. When logical 1 is received from the section 31, the clock signal -CLK is passed through. The output of the AND gate 35 is used for the clock signal for the device required for the registers of an operation control circuit.</p> |
