| 摘要 |
PURPOSE:To attain high speed operation of an integrated circuit by applying an output of the 1st clock driver circuit to the 2nd clock driver and applying an output of the 2nd clock driver to each block. CONSTITUTION:An output of the 1st clock driver 11 is fed to a logic section 13 and the 2nd clock drivers 31, 32, 33, 34, in parallel via a wiring 40. An output of the 2nd clock driver 31 is fed to a memory circuit 12 and a logic section 14 via a wire 41. An output of the 2nd clock driver 32 is fed to logic sections 15, 16 via a wire 42. An output of the 2nd clock driver 33 is fed to a logic section 17 via a wiring 43. An output of the 2nd clock driver 34 is fed to logic sections 18, 19 via a wiring 44. |
