I/O CONTROLLER FOR MULTIPLE DISPARATE SERIOAL MEMORIES WITH A CACHE

摘要

An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.