| 摘要 |
PURPOSE:To conduct efficiently the test by eliminating error processing even if an error is detected as to the address where an error takes place as the result of test of the pre-stage. CONSTITUTION:The content of an address register 10 is given to a memory 50 to be tested and an operating mode memory 14. In writing a data to the memory 50, a write data is set to a write data register 11 and in reading the memory 50, an expected value data is set to the register 11. The data read from the memory 50 is set to a read data register 12. A read date check circuit 13 discriminates whether or not the content of the register 12 is coincident with the expected data of the register 11 when the read data of the memory 14 is zero. When the read data of the memory 14 is logical 1, the circuit 13 is not operated. When the circuit 13 decides dissidence, the generation of error is informed to a processor controlling the test equipment. When generation of error is informed, error processing is executed. |
