发明名称 CLOCK SIGNAL DISTRIBUTION SYSTEM
摘要 <p>PURPOSE:To omit the resetting of the delay time and to attain application even to a slot-free type system by providing a delay circuit in consideration of the delay time on a mother board and supplying the clock signals of different phases. CONSTITUTION:A mother board 20 is drivded into three groups, and T1 shows the delay time of transmission on the board 20 for PB1-5. While T2 shows the delay time of transmission for PB5-9 respectively. The delay times of delay circuits 3 and 4 are set at T2 and T1+T2 respectively. The signal delivered from an oscillation circuit 1 is divided by a dividing circuit 2, and a delay T2 is produced at the circuit 3 together with a delay T1+T2 produced at the circuit 4. Therefore the output of the circuit 4 is transmitted as it is to the PB1; while the output of the circuit 2 is delivered as it is to the PB9. Thus T1+T2 is added to the PB9, and waveforms of PB1, 5 and 9 have the same phase. This omit the resetting of the delay time, and the synchronizing clock signals are obtained in each group on the board 20. This method can be applied even to a slot-free type system.</p>
申请公布号 JPS60256827(A) 申请公布日期 1985.12.18
申请号 JP19840113040 申请日期 1984.06.04
申请人 OKI DENKI KOGYO KK 发明人 SATOU NOBUYUKI;YAMAMOTO TAKEAKI;KAWAI HIDEAKI
分类号 G06F1/10;G06F1/04 主分类号 G06F1/10
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