发明名称 |
Vertical synchronisation pulse separator. |
摘要 |
<p>A vertical synchronisation separator includes an up/down counter which counts up when a composite sync signal fed to its input has one logic state and counts down when the composite sync signal has a second logic state, a decoder in the form of a gating circuit providing a logic (1) output when the count of the up/down counter exceeds a predetermined count.</p> |
申请公布号 |
EP0164978(A1) |
申请公布日期 |
1985.12.18 |
申请号 |
EP19850303882 |
申请日期 |
1985.06.03 |
申请人 |
MOTOROLA, INC. |
发明人 |
JOBLING, DAVID TREVOR;NEWTON, ANTHONY DAVID |
分类号 |
H04N5/10;G01R29/027;(IPC1-7):H04N5/10;H03K21/00 |
主分类号 |
H04N5/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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