| 摘要 |
PURPOSE:To avoid a latch up phenomenon while eliminating an useless region by a method wherein a pair of P-channel region and N-channel region comprising a supplementary MOS transistor array is separated from each other at an interval to provide a wiring region in the interval. CONSTITUTION:A supplementary array is composed of a P-channel region 6 provided with multiple P-channel MOS transistor 3P1, another P-channel region 1 formed of multiple P-channel MOS transistor 1P1-1Pn, an N-channel region 2 provided with multiple N-channel MOS transistor 1N1-1Nn and another N-channel region 7 formed of multiple N-channel MOS transistor 4N1. Next a wiring region 5 is provided to connect those transistors with each other so that the region 5 may be located in the gap between the regions 1 and 2 with through holes 20-23 penetrating thereinto through which the transistors in the regions 1, 2 are connected with each other. Later these transistors may be connected with the other transistors in the regions 6, 7. |
