| 摘要 |
PURPOSE:To reduce the overall area of an output circuit while maintaining the speediness of operation of the output circuit by reducing the area of a P channel transistor (TR) connected in parallel to an N channel TR which inverts an input. CONSTITUTION:Two N channel CH TRs 4 and 2 are connected in series and a PCH TR5 which has less area than the TRs 4 and 2 is connected in parallel to the TR4. The input signal is inputted to the gate of the TR4 through an inverter 6 and to the gates of the TRs 2 and 5 directly, and led out of the connection point of the TRs 4 and 2 to an external connection terminal 3. When the input signal varies from a level H to a specific level L, the TRs 4 and 5 turn on and the output signal led out to the terminal 3 varies to a specific level H. In this case, the TR5 compensates a deficiency in the leading edge level of the TR4 and raises it to the specific level H and the area of the Tr5 may be 0.2-0.3 times as large as those of the TRs 4 and 2, so the overall area of the circuit is reduced. |
