发明名称 HYSTERESIS CIRCUIT OF COMPLEMENTARY MIS TRANSISTOR
摘要 PURPOSE:To easily set a hysteresis loop with simple constitution by selecting properly values of a resistance connected in parallel to a PMOS transistor (TR) and a resistance connected in parallel to an NMOSTR. CONSTITUTION:When an input signal falls from a high level to a low level, the potential at a point M varies from a low level to a high level with a transfer characteristics Mu which is lower than the transfer characteristic Md at the point M in the low-to-high level transition of the input by a value depending upon the voltage drop across a resistance R1. Then when the input falls to a level low enough to invert the output of an inverter composed of trailing P2 and N2 to a low level after the potential at the point M is received, a PMOSTRP12 turns on to short-circuit the R1 again, and an NMOSTRN12 turns on to make R2 effective instead. At this time, the potential at the point M draws what is called a hysteresis loop with different routes as shown by the transfer characteristic Md at the time of low-to-high level variation of the input signal and the transfer characteristics Mu at the point M at the time of high-to-low level variation of the input signal. Further, values of R1 and R2 are adjusted to easily specify the width of hysteresis.
申请公布号 JPS60254911(A) 申请公布日期 1985.12.16
申请号 JP19840111406 申请日期 1984.05.31
申请人 FUJITSU KK 发明人 TANIZAWA SATORU
分类号 H03K3/353;H03K3/3565 主分类号 H03K3/353
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