发明名称 GATE ARRAY LSI DEVICE
摘要 PURPOSE:To increase the degree of freedom in logic design by a method wherein all of input and output terminals of a basic cell are made as the external terminals of a macro cell. CONSTITUTION:The final step latch part is composed of basic cells 1 and 2, and all of the input and output terminals are outputted as external terminals PR, M1, XQ, Q, M2, and CR. Since independent basic cells have been provided in a macro cell, connection of one input terminal M1 of the basic cell 1 to one of the input terminals A1, A2, and A3 of an independent basic gate 7 enables the monitor output terminal AX of the terminal M1 to be provided without exerting any effect on macro cell performance.
申请公布号 JPS60254632(A) 申请公布日期 1985.12.16
申请号 JP19840109468 申请日期 1984.05.31
申请人 FUJITSU KK 发明人 TANIZAWA SATORU
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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