发明名称 |
ARITHMETIC UNIT FOR SUM OF PRODUCT |
摘要 |
PURPOSE:To reduce only one adder as compared to an ordinary unit and to shorten an arithmetic processing time by adding the outputs of an accumulator by a Wallace tree adder together with the addition of partial products. CONSTITUTION:Input data to be the 1st data and factor data to be the 2nd data are supplied to terminals 1a, 1b respectively. A partial product formation circuit 2 forms the partial products of respective data on the basis of the Booth's method of 2 bits and the Wallace tree adder 7 adds the outputs of the accumulator 6 simultaneously with the addition of the partial products. The output of the Wallace tree adder 7 is supplied to a carry foreseeing adder 4 and its outputs are accumulated and outputted in/from the accumulator 6 as the calculated result for the sum of products. Said operation is sequentially repeated and the calculated result for the sum of products of all data is outputted. |
申请公布号 |
JPS60254373(A) |
申请公布日期 |
1985.12.16 |
申请号 |
JP19840111499 |
申请日期 |
1984.05.31 |
申请人 |
NIPPON PRECISION CIRCUITS KK |
发明人 |
TAKEDA MINORU;TAKAHASHI MASAYUKI |
分类号 |
G06F7/533;G06F7/508;G06F7/52;G06F7/544;G06F17/10;G06F17/16;H03H17/02 |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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