| 摘要 |
PURPOSE:To execute semaphore operation processing and CPU processing other than semaphore operation in parallel by accessing a common memory of CPUs excluded from semaphore processing even at the semaphore operation between specific CPUs. CONSTITUTION:When a CPU1 requests a certain operation to a CPU3, a READ MODIFY WRITE command (generally, a TAS instruction) is outputted to a certain specific address in the common memory 5, and if the contents of address ''X'' are ''0'', ''1'' is written. If ''1'' is recognized in a read cycle, data is not inverted in the write cycle in the address ''X''. Although the CPU3 can not access the common memory 5 during the execution of the TAS instruction by the CPU 1, the common memory 5 can be accessed by forming signal lines 6B, 7B. |
