| 摘要 |
PURPOSE:To reduce the scale of a circuit and to simplify it by detecting dissidence between bits of data read out in bit series during a communication between exchanges, and selecting an input state before or after the dissidence by a selecting means according to the detection output and sending out the selection output as control information. CONSTITUTION:Data bits read out of a memory 10 in bit series are supplied to one input terminal of an exclusive OR circuit 13 immediately, and delayed by one-bit time through a one-bit delay circuit 15 and supplied to the other input terminal of the exclusive OR circuit 13. A signal indicating whether there is dissidence between successive bits is outputted by the circuit 13 as a result of said bit processing. Bits inputted to a selector 14, i.e. input bits before or after dissidence are outputted selectively with the select signal from a flip-flop circuit 17 to the selection control input terminal of the selector 14, and the selection output signal is supplied as control information to an exchange (not shown in figure). Therefore, a bit change detection processing circuit is simplified. |
