发明名称 MEMORY ACCESS CONTROL SYSTEM
摘要 PURPOSE:To discriminate easily the generating source of an access error by providing a control table setting up I/O device identifying information in a storage part, and using an access-exclusive bus line in a common bus to access the control table. CONSTITUTION:An address in a memory 4 is selected by address data Z in an address register 8 of a channel device CH0 and data F in the memory 4 are written in a disc 10 through a bus 9. If a writing error is generated, an error signal is informed to a processor 1. A discrimination part 12 checks the bits B6, B7 of a register 13 and extracts a identification code I'0 in the control table 6 through a common bus 3. Consequently, the generating source of an access error generated at the time of memory access can be easily discriminated.
申请公布号 JPS60254348(A) 申请公布日期 1985.12.16
申请号 JP19840111274 申请日期 1984.05.31
申请人 FUJITSU KK 发明人 NISHIMURA NAOYUKI;SHIBATA TOMOHITO
分类号 G06F12/16 主分类号 G06F12/16
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