发明名称 PREPROCESSING SYSTEM FOR DATA TRANSMISSION
摘要 PURPOSE:To shorten the time of preprocessing prior to normal data transmission by providing the function of a frame header to plural time slots which have specific intervals. CONSTITUTION:A local area network consists of a system control node SV1' and normal nodes N2'-N6', and communications between the system control node and respective nodes are made by using headers SV1' and N2', SV1' and N3'... SV1' and N6' of a frame consisting of plural timer slots in the preprocessing prior to the normal data transmission of the transmission system to perform initial startup processing. In this case, the intervals of the time slots are determined on the basis of the transmission speeds of respective transmission lines and the processing speed of the processor of the SV1'. Therefore, this frame is only transmitted once through a system transmission line to complete the preprocessing, and the preprocessing time is shortened to one sixth as long as before.
申请公布号 JPS60254849(A) 申请公布日期 1985.12.16
申请号 JP19840111298 申请日期 1984.05.31
申请人 FUJITSU KK 发明人 YAMADA ISAO
分类号 H04L12/43 主分类号 H04L12/43
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