| 摘要 |
PURPOSE:To suppress the increase of hardware and also to generate an error with the designated timing by providing a false fault register, an execution instruction counting part, a cycle counting part and then an error status register respectively. CONSTITUTION:The output of a false fault contents register 1 is supplied to an error status register 5 via AND gates 511-51n. The outputs of an execution instruction counting part 3 and a cycle counting part 4 are supplied to the register 5 via an AND gate 43 and gates 511-51n. Then the output of the register 5 is supplied to an error processing part 6 via an OR gate 61. |
