| 摘要 |
PURPOSE:To speed up memory access by generating memory addresses at the same time with a simple circuit constitution by providing input and output registers and adders and by controlling the adders by the output of a control circuit. CONSTITUTION:The address generator of a data processor is provided with 2<n> units of adders 5-1-5-4, and corresponding to those adders 5-1-5-4, shift registers 6-1-6-4 inputting startig addresses S, and shift registers 8-1-8-4 inputting distance data D between elemtnts through registers 7-1-7-4 are provided. Futher, a control circuit 10 controlling the registers and adders 5-1-5-4 is provided; the registers 6-1-6-4 set the address S, and the registers 8-1-8-4 set inputs 0-4D or 2<n>xD pieces of inputs by the data S. According to the 1st and 2nd timing signals from the circuit 10, outputs of the adders 5-1-5-4 are controlled to generate memory addresses by registers 9-1-9-4 at the same time. |
