发明名称 MEMORY INTEGRATED CIRCUIT PROVIDED WITH LATCH FUNCTION
摘要 PURPOSE:To make a write cycle small, and to execute a write operation of a memory IC at a high speed by adding a latching circuit for using an internal shaping pulse which has shaped a write pulse, as a clock, to an address and write information input part of the memory IC. CONSTITUTION:A write pulse inputted to a write pulse input terminal 12 generates a prescribed pulse width by a write pulse shaping circuit 25, uses it as an internal shaping pulse, and also an output of the write pulse shaping circuit 25 becomes a clock input of an address latching circuit 20 and a data latching circuit 21. Since an information input is latched, an operation can be executed without affecting the next cycle, if the max value is secured with regard to an information input holding prescribed value. Therefore, a write cycle can be made small by a difference of the max value and the min value of the information input.
申请公布号 JPS60253086(A) 申请公布日期 1985.12.13
申请号 JP19840110617 申请日期 1984.05.30
申请人 NIPPON DENKI KK 发明人 UMEDA JIYUNZOU
分类号 G11C11/413;G11C7/00 主分类号 G11C11/413
代理机构 代理人
主权项
地址