发明名称 DECODING SYSTEM OF DIGITAL DATA
摘要 PURPOSE:To use both synchronizing and address codes, and to inspect an advance of the address code by detecting a position of the synchronizing code if an input data, increasing by one each whenever a block address is shifted to the next address, and arranging the input data by using the synchronizing code. CONSTITUTION:A synchronizing code decoder 5 brings a data to a barrel rotation by circuits 3, 4 in accordance with a phase of a detected synchronizing code, and address decoders 7, 8 decode an output of the circuits 3, 4, execute a single error identification and a correction, and apply an end flag. Two error detections are indicated by different flags. An address comparing circuit 9 compares two continuous block addresses of the decoders 7, 8, and advances a block address by one each by an address advancing circuit 10. A result of comparison is supplied to a synchronizing code and address code analyzing circuit 6, and when the address of the latter is more by one than the former, a code from the decoder 8 and a data start pulse from the decoder 5 are loaded to a synchronizing code and address code fly-wheel circuit 11. The circuit 6 supplies a signal to a circuit 12 and confirms a correct rotation of the data.
申请公布号 JPS60253065(A) 申请公布日期 1985.12.13
申请号 JP19850104357 申请日期 1985.05.16
申请人 SONY KK 发明人 JIEEMUSU HETSUDOREE UIRUKINSON
分类号 G11B20/10;G11B20/12;G11B20/18;H04N5/935;(IPC1-7):G11B20/10 主分类号 G11B20/10
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