发明名称 VECTOR DATA PROCESSOR
摘要 PURPOSE:To attain plural arithmetic executions by one vector arithmetic instruction by executing an optional arithmetic for a specific element in vector data having a long vector length in accordance with the element. CONSTITUTION:Operators such as modification bits M1-M3 of R1-R3 parts, an instruction conversion code C and a command Ci are added to the R4 part of a vector instruction. In a pipe-line operation stage, respective elements of data A and that of data B are read out from a vector register specified by the R3 part of the vector instruction and a register specified by the R2 part respectively to a stage register 1 for arithmetic stages. Then, the operator is read out from the vector register specified by the R4 part of the vector instruction to the register 1 in accordance with the element and sent to an arithmetic unt 2 and arithmetic specified by the operator is executed in accordance with respective elements.
申请公布号 JPS60251470(A) 申请公布日期 1985.12.12
申请号 JP19840107739 申请日期 1984.05.28
申请人 FUJITSU KK 发明人 SASAKI YUUICHI;NAKATANI SHIYOUJI
分类号 G06F9/38;G06F17/16 主分类号 G06F9/38
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