| 摘要 |
PURPOSE:To attain high speed processing through a so-called pipe-line processing by cascade-connecting comparator elements at the processing of respective elements constituting a set A and the ones constituting a set B. CONSTITUTION:The comparator elements 11-14 are cascade-connected to constitute a set processing unit. Each comparator element is constituted so as to input an element input (ain) signal for inputting an element ak, an element input (bin) signal for inputting an element bl and a control input signal (cin) and output an element output (bout) signal and a control output signal cout. Elements b1, b2- are successively supplied from the element input terminal of the leftmost comparator element 11 with a prescribed priod. On the other hand, the elements a1-an are applied from respective element input terminals to respective comparator elements 11-14 almost fixedly. When an element b1 is supplied to the element 11 in the 1st cycle, logic ''0'' is applied as its control input signal cin, and if a1=b1, the element b1 is outputted as the signal bout.
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