| 摘要 |
A digital phase detector for processing digital signals consisting of words containing more than 10 bits eliminates the need for a large read-only memory for arc tan values and requires only individual read-only memories for the arc tan values 2-r, where r=1 . . . n. n-1 like stages are provided each of which consists of an adder, a subtracter, two constant multipliers for the factor 2-r, and three changeover switches. The nth stage contains a constant multiplier for 2-n, a subtracter, and a changeover switch. The outputs of one of the changeover switches in each of the like stages and of the changeover switch in the nth stage are coupled to the inputs of a multiple-input adder whose output provides the phase detected digital signal. In a second variant of the solution, only j stages contain the above-mentioned subcircuits, while the other stages are simplified to form cells each of which contains only one constant multiplier, a subtracter with associated changeover switch, and an inverter. The outputs of this inverter are connected to the input of a register having its parallel output coupled to one of the inputs of the multiple-input adder. |
