发明名称 RETRY CONTROL SYSTEM
摘要 PURPOSE:To eliminate access required to a main memory in a retry control mode and especially to avoid an access fault of another processor in a multi- processor system, by providing a memory means for saving in addition to the main memory for retry control. CONSTITUTION:A saving register 24 is provided within a processor 2. Then the contents of an instruction counter 22 and a register 21 are saved to the register 24 every time the execution of a program proceeds to a check point inserted into the program. The saved is carried out for every check point and then just repeated as long as a normal state lasts. A machine check is carried out when an error is detected. The saved data is sent back to the counter 22 and the register 21 from the register 24 when the machine check is over. The use of a recovery control function can be limited with mode designation. A memory 25 set outside the processor 2 is also available in place of the register 24.
申请公布号 JPS60250440(A) 申请公布日期 1985.12.11
申请号 JP19840106128 申请日期 1984.05.25
申请人 FUJITSU KK 发明人 OKAMOTO TETSUO
分类号 G06F11/14 主分类号 G06F11/14
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