Integrated circuit testing arrangements.

摘要

An integrated circuit testing arrangement of the kind using the level sensitive scan design technique wherein there is used a test generator (7) of such a form that each cone of the combinational logic (1) of the integrated circuit is exhaustively tested. In a preferred arrangement the test generator (7) comprises a maximal length linear feedback shift register (LFSR), i.e. en LFSR which has 2<N> -1 different states where N is the number of stages in the LFSR, and the LFSR is chosen so that 2<N> -1 and the number of elements in the scan path (5) are relatively prime.