Method of manufacturing CMOS devices.

摘要

A method of forming an insulation sidewall spacer in a semiconductor structure which has a layer of polycrystalline silicon (23) overlain by a layer (121) of material which etches more slowly than polycrystalline silicon for a selected etchant. Etching the semiconductor structure causes a portion of the second layer to overhang a portion of the first layer. By conformally depositing a layer of insulation on the etched semiconductor structure and then vertically etching the resulting structure, insulation sidewall spacers (71) are formed which fill the region under the overhanging portion of the second layer thus reducing the capacitance between the overhanging portion of the second layer and other portions of the semiconductor structure.