| 摘要 |
PURPOSE:To decrease the data transfer frequency by connecting an N/2-bit additional register in series and circularly to an N-bit register which can shift data in both directions and controlling the selectors corresponding to each bit of the additional register. CONSTITUTION:An N-bit register 7 which stores the output of an operator can shift its data in both directions. An N/2-bit additional register 8 is connected in series and circularly to the register 7. A selector (not shown in the figure) decides the number of series shift bits in response to each bit of the register 8. Then a shifter and an accumulator ACC are unified. When a bit of the latter half of an address (i) in a RAM and three bits of the first half of an address (j) are stored in an address (k) as a work with N=4, for example, satisfied, the contents of the address (i) are transferred to the ACC and shifted right by a bit. Then the contents of the address (j) are transferred to the ACC and shifted right by a bit. The results of these shifts are transferred to the address (k).
|
