| 摘要 |
The applique rate converter permits a digital multiplexer to support any data rate less than half of its input port design rate. The applique rate converter develops a composite data stream consisting of alternate data bits and data boundary bits. The data boundary bits change state at each new data bit (corresponding to a change in the data clock.) The composite bit stream is increased to the output data rate by means of a circuit called the 'synchronizer'. At the demultiplex side of the applique, the data is separated from the composite stream by a decoding process and, if necessary, the data stream is rate smoothed. The major sections of the applique rate converter are the 'synchronizer' at the multiplex side and the data separator and rate smoothing circuits at the demultiplex side.
|
