发明名称 CHARACTER BROADCAST RECEIVER OF ENCODING TRANSMISSION SYSTEM
摘要 PURPOSE:To use efficiently the memory space of a display memory to reduce the cost by providing an address converting circuit for exchange of character and pattern information and color and functional block information in a display control circuit. CONSTITUTION:Eight dynamic RAMs (DRAMs) are used as a display memory 20, and each of them can constitute four pictures and one picture. When information is read out from the display memory 20, address conversion from character and pattern information to color and functional block information is performed by an address converting circuit 22. The output of the address converting circuit 22 is applied to a display memory address circuit 23, and a row address and a column address to DRAMs 20 are switched and given. A series of these timing controls are performed consistently by timing pulses from a timing generating circuit 24.
申请公布号 JPS60249489(A) 申请公布日期 1985.12.10
申请号 JP19840106797 申请日期 1984.05.24
申请人 MITSUBISHI DENKI KK 发明人 SHIBAZAKI TAKESHI
分类号 H04N7/083;G09G1/06;G09G5/00;H04N7/025;H04N7/03;H04N7/035;H04N7/087;H04N7/088 主分类号 H04N7/083
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