发明名称 VERTICAL DEFLECTING CIRCUIT
摘要 PURPOSE:To reduce the power consumption of a vertical deflecting circuit by using the bias current of a transistor TR of a vertical outputs stage as a centering current supplied to a vertical deflecting coil. CONSTITUTION:In the vertical deflecting circuit, a collector bias current base on a base bias voltage set by resistances 23, 24, and 25 is always flowed to the collector of a TR22 which is the vertical output element, and this bias current is used as the centering current of a vertical deflecting coil 26. Thus, the bias current is used as the centering current to prevent the loss of the power consumption in the vertical deflecting circuit.
申请公布号 JPS60249474(A) 申请公布日期 1985.12.10
申请号 JP19840106218 申请日期 1984.05.25
申请人 SONY KK 发明人 TAGAWA SUSUMU
分类号 H04N3/227;H01J29/76 主分类号 H04N3/227
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