| 摘要 |
PURPOSE:To improve measuring efficiency by providing an OR circuit which detects the defect of the other semiconductor element from the dissidence signal from plural comparators so that the plural elements to be measured can be simultaneously measured. CONSTITUTION:A pattern generator 2 applies test pattern data (a) to the elements 31-3n to be measured and applies expected value data (c) to a comparator 41 by the command from a controller 1. The elements 31-3n output data b1-bn and apply the same to the comparators 41-4n according to said data. Acceptance or reject data d1 is outputted from the comparator 41. The controller 1 discriminates the acceptance or reject of the element 31. The comparators 42-4n compare the output b1 from the element 31 and the output data b2-bn from the elements 32-3n in parallel with said operation and feed the dissidence signals d2-dn to the OR circuit in the stage of dissidence. The circuit 5 generates a signal (e) in accordance with one dissidence signal and transmits the signal to the controller 1.
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