SAMPLING CLOCK REPRODUCING CIRCUIT

摘要

PURPOSE:To obtain a sampling clock with a phase optimum to a data sampled actually by selecting any one clock among plural clocks with different phase used in detecting a phase distributed data. CONSTITUTION:An oscillating signal of 8/5fSC (fSC is a frequency of chrominance subcarrier) is fed from a terminal 21 to a delay pulse generating section 22 and the signal is converted into plural clocks CK0-CKN with different phases. The clocks CK0-CKN are inputted to a data selector 23, any one clock is selected and led out as a sampling clock SAS. The selector 23 is controlled by a selection data from an optimum phase decision section 33 so as to decide a selection clock. On the other hand, a video signal VD including a character multiplex signal is fed to an AND circuit 26 from a terminal 25 and a received clock run in signal or a succeeding data are outputted from the circuit 26.