发明名称 DECIMAL MULTIPLYING CIRCUIT
摘要 PURPOSE:To perform decimal multiplication processing speedily through a small number of steps by calculating some of partial multipliers of a multiplicand previously, and performing arithmetic among proper partial multipliers according to a multiplier and calculating multiples of the multiplicand. CONSTITUTION:A register 11 holds the multiplicand and its multiples which are twice, four times, and eight times. A register 2 holds the sum of partial products being calculated, and makes a shift in a next step. A register 3 holds the multiplier and also performs shifting operation associatively with the register 2. A selecting circuit 12 is controlled by a control circuit 13 to select a specific multiple in the register 11 and addition or subtraction according to the numeral of the lowest-order position of the register 3. The decimal arithmetic circuit 5 adds the specific multiple selected by the circuit 12 to the output of the register 2 to supply the sum of partial products to the register 2 and also performs multiple calculation and the addition or subtraction of the specific multiple. Thus, decimal multiplication is performed through a small number of steps.
申请公布号 JPS60247735(A) 申请公布日期 1985.12.07
申请号 JP19840105176 申请日期 1984.05.24
申请人 NIPPON DENKI KK 发明人 CHII TOSHIROU
分类号 G06F7/496;G06F7/52;G06F7/527 主分类号 G06F7/496
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