| 摘要 |
PURPOSE:To prevent destruction or mis-reading of storage information and to attain high speed operation even if a delay time of a common source line of a differential amplifier circuit is large by operating a data line high potential compensating circuit or connecting the circuit to input/output lines after the amplified state of a data line is detected. CONSTITUTION:Two circuits DA1 whose output goes to a low level when a potential of a data line is lower than a reference level Vref1, a NAND circuit NAND1 inputting the output of the two circuits, and an AND circuit AND1 obtaining a NAND output, a pulse PHIs and an AND output are provided to a detection circuit 1. No AR is operated and input/output lines are not connected before the signal amplification by an SA is not executed sufficiently and the storage information is not destructed and no mis-read is caused. Since the AR operation and the connection with the input/output line are not delayed unnecessary, high speed memory operation is attained. |
