| 摘要 |
PURPOSE:To make a response time constant and improve timing accuracy, and expand an application range by performing counting operation in every instruction cycle at a request for interruption and accepting the interruption when the counted value attains to a specific value. CONSTITUTION:A request flag 2 is set in synchronism with the rising of an interruption request signal IRQ and its output signal IF goes up to ''1'', and a counter 3 in the reset state is actuated to count up by one for every machine cycle. When the specific number of machine cycles from the start of counting to the acceptance of interruption is set to ''8'', instructions being executed at present are executed continuously and automatically up to a final state even if an input for an instruction decoder 9 varies. Then when the counter counts up to the specific value ''8'', the output CMP of a comparator 5 goes up to ''1'' and a gate 7 is opened to output an interruption acceptance request signal IN=1, so that a decoder 9 starts accepting the interruption. At this time, any instruction code is disregarded even if inputted to the decoder 9, and an interruption ACK signal is generated to reset the flag 2, thus completing a series of interruption processes.
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