| 摘要 |
PURPOSE:To realize a high-speed operation for an MIS memory circuit, by providing a switching means to give a short to a pair of common data lines during the nonselection of chip or a switching means to give the same bias potential to the above-mentioned common data lines during the nonselection of chip. CONSTITUTION:The memory cells 5a-5d are composed of the MISFETQ64 and Q65 forming a fip-flop circuit, the load means R1 and R2 plus the transfer gate MISFETs Q66 and Q67 which are provided to the input/output terminal of the flip-flop circuit and then controlled by the outputs X1-Xi of the X address decoder circuit 4. The MISFETQ74 functioning as a duplex switch is provided to secure the equal potential between a pair of the common data lines CD0 and CD1. The MISFETQ74 is turned on during the nonselection of chip to eliminate forcibly the difference of holding level between the lines CD0 and CD1. As a result, a high-speed operationcan be secured for the next reading. |
